Rajendra, whose field is electronics engineering and computer science, assists in the preparation and prosecution of U.S. and international patent applications for clients in the software and electronics technology fields.
Rajendra's areas of technical experience include design, architecture and development of software systems that include databases and database applications, text search, information retrieval, image processing, bioinformatics, programming language design and implementation, social networking systems, artificial intelligence, machine learning, deep learning, neural networks, blockchain, data stream query processing, autonomous vehicles and VLSI design tools for electronic design automation.
Prior to joining Fenwick, Rajendra was a software engineer for over twelve years with leading technology companies including IBM, Verity (acquired by Autonomy) and emerging Silicon Valley-based startups.
Rajendra is a recognized inventor having been awarded four patents. He is a named inventor on several other patent applications and has had his work published in numerous books, conference proceedings and leading peer-reviewed journals.
Co-inventor of Patents
- Patent No. 5,983,016: Execution engine in an object modeling tool
- Patent No. 6,505,211: Method for providing persistence for Java classes where the persistence semantics may be orthogonal to the class definition
- Patent No. 6,898,782: Reference-based associations using reference attributes in an object modeling system
- Patent No. 6,973,572: Signature hash for checking versions of abstract data types
- Patent No. 10,157,195: External system integration into automated attribute discovery
- Patent No. 10,671,575: External system integration into automated attribute discovery
- “Fenwick Secures Political Asylum for Client Facing Persecution in Guatemala,” Fenwick & West Pro Bono Blog, March 2017 (co-author)
- "Section 102 and the MPEP," Prior Art & Obviousness 2009, Practising Law Institute, No. G-975, 2009
- “Consideration of Prior Art by Courts Does Not Bar Subsequent Considerations in Reexaminations,” Intellectual Property 2008/2009 Winter Bulletin, Fenwick and West, 2008
- “The Propel Distributed Services Platform,” Proceedings of the 27th International Conference on Very Large Data Bases, pp 671 – 674, 2001 (co-author)
- “Efficient Compilation of Concurrent Call/Return Communication in Actor-based Programming Languages,” Third International Conference on High Performance Computing, pp 62-67, Trivendarum, India, IEEE Computer Society, 1996
- “Actor Languages for Specification of Parallel Computations,” DIMACS: Series in Discrete Mathematics and Computer Science, vol. 18, pp 239-258, American Mathematical Society, 1995 (co-author)
- “A Methodology for Programming Scalable Architectures,” Journal of Parallel and Distributed Computing, Vol. 22, September 1994
- “Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors,” VLSI Design, Gordon and Breach Science Publishers, Vol. 1, No. 2, 1994
- “Abstraction and Modularity Mechanisms for Concurrent Computing,” IEEE Parallel and Distributed Technology, Systems and Applications, Vol. 1, No. 2, pp 3-15, IEEE Computer Society, May 1993 (Also published as book chapter in Research Directions in Concurrent Object-Oriented Programming, MIT Press)
- “A Linguistic Framework for Dynamic Composition of Dependability Protocols,” Conference on Dependable Computing for Critical Applications (DCCA-3), pp 197-207, International Federation of Information Processing Societies, Palermo (Sicily), Italy, September, 1992
- “Distributed Execution of Actor Systems,” Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, Vol. 589, pp 1-17, Springer-Verlag, 1992 (co-author)
- Goldman Sachs
- Perceptive Automata
Education & Admissions
J.D., magna cum laude, Santa Clara University
Ph.D., Computer Science
University of Illinois at Urbana-Champaign
M.E., Systems Science and Automation
Indian Institute of Science, Bangalore
B.E., Electronics Engineering
Admitted to practice in California
Registered to practice before the U.S. Patent and Trademark Office