Rajendra Panwar, Ph.D.

Associate, Intellectual Property  

Mountain View 650.335.7107


Rajendra Panwar, whose field is electronics engineering and computer science, assists in the preparation and prosecution of U.S. and international patent applications for clients in the software and electronics technology fields.

Rajendra's areas of technical expertise include design, architecture and development of software systems that include database applications, extensions to SQL/database engines, text search and information retrieval, object-oriented modeling tools, programming language design and implementation, and VLSI design tools for electronic design automation.

Prior to joining Fenwick & West, Rajendra was a software engineer for over twelve years with leading technology companies including IBM, Verity (acquired by Autonomy) and emerging Silicon Valley-based startups.

Rajendra is a recognized inventor having been awarded four patents. He is a named inventor on several other patent applications and has had his work published in numerous books, conference proceedings and leading peer-reviewed journals.


  • Robert Hulse, Puneet Sarna & Rajendra Panwar, "Section 102 and the MPEP", Prior Art & Obviousness 2009, Practising Law Institute, No. G-975, 2009
  • “Consideration of Prior Art by Courts Does Not Bar Subsequent Considerations in Reexaminations” Intellectual Property 2008/2009 Winter Bulletin, Fenwick and West LLP.
  • The Propel Distributed Services Platform, Proceedings of the 27th International Conference on Very Large Data Bases, pp 671 – 674, 2001.
  • Efficient Compilation of Concurrent Call/Return Communication in Actor-based Programming Languages, Third International Conference on High Performance Computing, pp 62-67, Trivendarum, India, IEEE Computer Society, 1996.
  • Actor Languages for Specification of Parallel Computations, in G. E. Blelloch, K. Mani Chandy and S. Jagannathan (editors), DIMACS Series in Discrete Mathematics and Computer Science, vol. 18, pp 239-258, American Mathematical Society, 1995.
  • A Methodology for Programming Scalable Architectures, Journal of Parallel and Distributed Computing vol. 22, September 1994.
  • "Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors,” VLSI Design, Gordon and Breach Science Publishers, Vol. 1, No. 2, 1994, pp 127-154.
  • Abstraction and Modularity Mechanisms for Concurrent Computing, IEEE Parallel and Distributed Technology, Systems and Applications, vol. 1, no. 2, pp 3-15, IEEE Computer Society, May, 1993. Also published as book chapter in Research Directions in Concurrent Object-Oriented Programming, MIT Press.
  • A Linguistic Framework for Dynamic Composition of Dependability Protocols, Conference on Dependable Computing for Critical Applications (DCCA-3), pp 197-207, International Federation of Information Processing Societies, Palermo (Sicily), Italy, September, 1992.
  • Distributed Execution of Actor Systems,  in D. Gelernter, T. Gross, A. Nicolau, and D. Padua (editors), Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 589, pp 1-17, Springer-Verlag, 1992.

Co-inventor of Patents

  • Patent No. 5,983,016: Execution engine in an object modeling tool.
  • Patent No. 6,505,211: Method for providing persistence for Java classes where the persistence semantics may be orthogonal to the class definition.
  • Patent No. 6,898,782: Reference-based associations using reference attributes in an object modeling system.
  • Patent No. 6,973,572: Signature hash for checking versions of abstract data types.