Jorge assists in the preparation and prosecution of U.S. and international patent applications for clients in a range of technology areas, including computer software, electronics, electromechanical, and medical devices industries. Jorge's areas of technical experience include electronic circuits, semiconductor fabrication, microfluidic devices, artificial intelligence, machine learning, blockchain, and autonomous vehicles.

While attending UCLA, Jorge worked at the university’s Nanostructure Devices and Technology Laboratory as a researcher in the area of nanoarchitectonics and nanotheranostics, interdisciplinary fields dealing with nanoscience, medical therapy and disease diagnostics. He also worked on experimentally developing 2D orthogonal nanowire fabrics and intrinsic switching devices formed within the fabrics for the implementation of digital circuits.

    • Publications
      • Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics, IEEE Transactions on Nanotechnology, 2012.
      • Heterogeneous Integration of Epitaxial Nanostructures - Strategies and Application Drivers, SPIE Optics and Photonic Meeting, 2012 Aug. 12-16.
      • On-Chip Variation Sensor for Systematic Variation Estimation in Nanoscale Fabrics, IEEE 12th International Conference on Nanotechnology, 2012 Aug. 20-23.
      • Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation, ACM Journal on Emerging Technologies in Computing Systems, 2012.
      • Smart Diagnostics Capsule with a Novel Antenna and Nano-Biosensors, presented at the 6th European Conference on Antennas and Propagation (EuCAP), 2012 March 26-30.
      • Integrated Nanosystems with Junctionless Crossed Nanowire Transistors, IEEE 11th International Conference on Nanotechnology, 2011, Aug. 15-18.
      • Nanoscale Application Specific Integrated Circuits, IEEE/ACM International Symposium on Nanoscale Architectures, 2011 June 8-9.
      • 3D Integrable Nanowire FET Sensor with Intrinsic Sensitivity Boost, IEEE International Conference on Integrated Circuit Design and Technology, 2011 May 2-4.
      • Parameter Variability in Nanoscale Fabrics: Bottom-up Integrated Exploration, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010 Oct. 6-8

    Education & Admissions

    J.D., University of California, Berkeley, School of Law

    M.S., Electrical Engineering
    University of California, Los Angeles

    B.S., Electrical Engineering
    University of California, Los Angeles

    Registered to practice before the U.S. Patent and Trademark Office


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